Hi,

We don't have any references for doing SPI communication using Bit-Bang. I would recommend that you use the MPSSE for SPI communication instead.   

To use I2C/SPI as a master (no slave functionality), see AN_135 MPSSE Basics and our existing MPSSE Example projects:
 
MPSSE Examples
 
There are two options to use I2C/SPI modes with the MPSSE engine:
 
a.   Use LibMPSSE libraries. Example code is provided with the download. Source code is also provided.
b.   Use D2XX drivers direct. Example code is shown at I2C / SPI. AN_108 Command Processor For MPSSE and MCU Host Bus Emulation Modes provides the necessary information.
 
Option b is the best option to use the D2XX drivers direct (no dependency on libMPSSE library).

Also please also note, SPI modes 1 and 3 are not supported with our MPSSE engine.
So please check that your SPI device doesn’t work with these modes.

You can find all the referenced documentation above, here

Hi,

yes, FT2232H is a high-speed device. The driver can only operate with 1ms latency minimum.

Best regards
FTDI Community

Hello,

There are 2 kinds of delays / pauses.

1. Occurs when FIFO switches from ping to pong buffer. There are 2 FIFO Buffers and when current one gets filled, hardware moves to second FIFO. There will be a brief delay during this period.
2. Occurs when a session is ended and a new session is created. This delay can be slightly larger than the above one.
A session will be ended when the length of transferred data equals with the stream length set by FT_SetStreamPipe API (if not in stream mode, then the length passed in Read Pipe API), or when an unaligned write happens.
 
Between the end of session and start of new session, there could be some delay as observed.

If the stream length is shorter, this delay will be seen often.
The recommended stream length is, several multiples of the FIFO size.
For example, if the FT600 configuration uses 4K FIFO size, it's best to make the stream length as multiples of 4K - Say 10 times or 100 times of 4K.
This way, instead of seeing a long delay every 4K, the long delay will happen only at 400K transfer boundaries.

The FPGA is expected to buffer at least a FIFO size worth of data so that the delay does not cause any issues such as overflow.

If you have any additional questions please contact us via email as we have already been in contact with you.

Best Regards,
FTDI Community

Hi,
If you use FT_SetBitMode to reset (zero for reset)   
https://ftdichip.com/wp-content/uploads/2023/09/D2XX_Programmers_Guide.pdf (Page 66, D2xx programmers guide)

Regards
FTDI Community

Hello,

Please provide the USBView details and screenshot for analysis.

Please send this via email to your local support team:

https://ftdichip.com/technical-support/

Best Regards,
FTDI Community

Hi,
We don't have any experience with "Linux Docker" although i note that they have a community page also.
https://www.docker.com/community/

Our D2xx driver as well as the libFT4222 files are available from our website   
https://ftdichip.com/drivers/
https://ftdichip.com/wp-content/uploads/2022/06/libft4222-linux-1.4.4.170.tgz

Regards
FTDI Community

Hello All,

We have a beta version of libMPSSE 1.0.4 which fixes all known issues.

Please contact support1@ftdichip.com for this version before we release it to our website.

Let us know if you have any feedback please.

Best Regards,
FTDI Community