Hello!
I just tried an USB 3.0 cable, the test program works now, albeit only channel 3 and 4 (probably messed something up with the configuration of channel 1 and 2, also the LED which indicates that frames are dropped is flashing permanently when viewing video from channel 3 and 4). But I was not able to reproduce the Verilog code to generate my own test patterns. So I have some questions:
1) How is a USB package containing a video frame set up? The datasheet (
https://www.ftdichip.com/Support/Documents/AppNotes/AN_434_FT602_UVC_Bus_Master_Sample.pdf) says that each frame starts with the header 0x0000_820C, 0xBABE_FACE, 0xBABE_FACE and ends with 0x55. It also states that the termination byte (0x55) is not sent to the USB host. But how does the FT602 know whether a received 0x55 is just another pixel data or the end of the frame?
2) The BE bus tells the FT602 how many bytes on the DATA bus are valid. Does this apply only to actual pixel data or also to header bytes?
3) How does the pattern generator tell the USB host that a pixel line of the frame is transmitted completely (hysnc)?
4) What is communicated via the I2C bus?
Thank you for your fast and helpful replies!