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Discussion - Hardware / About the input delay of FPGA when connecting FT601 with FPGA
« on: January 27, 2021, 11:49:53 AM »
Hi,
I am using the FT601 chip with Cyclone V GX FPGA.
I have difficulty in setting the input delay of FPGA's timing constraint.
In common definition of input delay, input delay = the time from clock rising to data stable (both clock and data are from FT601).
In FT601's datasheet, (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT600Q-FT601Q%20IC%20Datasheet.pdf)
In Figure 4.8 and Table 4.2, T1 and T2 give the AC timing of signals from FT601 to FPGA.
It seems that the data is stable between CLK's rising-T1 to CLK's rising+T2.
There's an sdc example in AN_421 FIFO Bus Master for FT60x (https://www.ftdichip.com/Support/Documents/AppNotes/AN_421_FIFO_Bus_Master_For%20FT60x.pdf)
The input delay max = CLK period - T1 = 10ns - 3ns = 7ns (for CLK = 100MHz)
I am confused about the input delay min = 6.5ns.
Since T2 is a minimal value, after CLK's rising+T2, the data of next cycle may be stable before the next CLK's rising-T1.
So I think the input delay min is T2 = 3.5ns.
Why the input delay min is 6.5ns in the AN_421?
Thanks,
Stanley
I am using the FT601 chip with Cyclone V GX FPGA.
I have difficulty in setting the input delay of FPGA's timing constraint.
In common definition of input delay, input delay = the time from clock rising to data stable (both clock and data are from FT601).
In FT601's datasheet, (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT600Q-FT601Q%20IC%20Datasheet.pdf)
In Figure 4.8 and Table 4.2, T1 and T2 give the AC timing of signals from FT601 to FPGA.
It seems that the data is stable between CLK's rising-T1 to CLK's rising+T2.
There's an sdc example in AN_421 FIFO Bus Master for FT60x (https://www.ftdichip.com/Support/Documents/AppNotes/AN_421_FIFO_Bus_Master_For%20FT60x.pdf)
Code: [Select]
set_input_delay -clock [get_clocks fifoClk] -max 7.0 [get_ports {RXF_N}]
set_input_delay -clock [get_clocks fifoClk] -max 7.0 [get_ports {BE[*] DATA[*]}]
set_input_delay -clock [get_clocks fifoClk] -min 6.5 [get_ports {RXF_N}]
set_input_delay -clock [get_clocks fifoClk] -min 6.5 [get_ports {BE[*] DATA[*]}]
The input delay max = CLK period - T1 = 10ns - 3ns = 7ns (for CLK = 100MHz)
I am confused about the input delay min = 6.5ns.
Since T2 is a minimal value, after CLK's rising+T2, the data of next cycle may be stable before the next CLK's rising-T1.
So I think the input delay min is T2 = 3.5ns.
Why the input delay min is 6.5ns in the AN_421?
Thanks,
Stanley