Hello,
Have you took a look at
TN_167 FTDI FIFO Basics?
This also includes software examples.
You must monitor the TXE# and RXF# flags.
The TXE# and RXF# outputs are the buffer status pins (flags).
For both Asynchronous and Synchronous FIFO modes, the status of the internal transmit and receive buffers must be monitored by the external FPGA or microcontroller to avoid buffer over run and data loss.
The TX buffer is used by data sent from the FIFO pins back to the host (write operation)
The RX buffer is used by data sent from the host to the FIFO output pins (read operation)
When the TXE# flag is low, this indicates there is enough internal transmit buffer space available for writing data back to the host. The USB host application code (VCP or D2XX for Async FIFO, D2XX for Sync FIFO) must constantly read incoming data from the device to keep the buffer from filling up.
When the RXF# flag is low, this indicates there is still unread data in the internal receive buffer remaining to be read by the downstream FPGA or micro. Instead of interpreting this flag as “receive buffer full”, the RXF# flag can best be thought of as “receive buffer not empty yet”. When the RXF# flag stays high, the last byte of data in the buffer remains on the data bus and does not change.
Here is some other useful information:
The 245 FIFO interface should only be written to when the TXE# pin is logic 0.
The TXE# pin will go to logic 1 and back to logic 0 for every byte latched in.
If the application on the PC never reads any data the buffer on the PC (64kbytes) and the buffer on the chip will become full.
When these buffers are full the TXE# line should remain at logic 1 until the application on the PC does a read to free up some space.
Some users report TXE# goes back to logic 0 after a brief period (actually matches latency timer).
This can result in data loss due to overrun.
To prevent this from happening the application on the PC should have set flow control for RTS_CTS flow control.
Although the hardware does not have RTS/CTS pins the driver does not know this, but it is now forced to monitor certain status bits, which allows the TXE# pin to be kept at logic 1 until space is made available.
Maybe there are other FTDI Community users who can help you further.
Best Regards,
FTDI Community