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Discussion - Software / Understanding FT232H buffer behavior
« on: April 16, 2019, 03:46:15 pm »
Hello,
I am currently trying to interface an FT232H with a ti microcontroller using the FT245 asynchronous interface. To optimize the throughput, I am trying to understand which buffers are involved when reading or writing to the FT232H.
Here is what I do not understand: The FT232H has two 1Kb read and write buffers. How is it possible to generate 64KByte USB packets from these buffers? For example, I am able to send a 64KByte USB packet from the PC host to the FT232H. I can see that this actually happens using Wireshark. This packet should pass over the wire in 1ms, correct? However, my processor needs 8.5ms to read this packet from bridge chip. How is this possible? Where is the data buffered during this time?
Thank you very much and best regards,
Bart
I am currently trying to interface an FT232H with a ti microcontroller using the FT245 asynchronous interface. To optimize the throughput, I am trying to understand which buffers are involved when reading or writing to the FT232H.
Here is what I do not understand: The FT232H has two 1Kb read and write buffers. How is it possible to generate 64KByte USB packets from these buffers? For example, I am able to send a 64KByte USB packet from the PC host to the FT232H. I can see that this actually happens using Wireshark. This packet should pass over the wire in 1ms, correct? However, my processor needs 8.5ms to read this packet from bridge chip. How is this possible? Where is the data buffered during this time?
Thank you very much and best regards,
Bart