FTDI Community
General Category => Discussion - Hardware => Topic started by: GabPGomes on April 28, 2023, 10:02:41 PM
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Hi, this topic is not a question, it's just a report of what I've done. I hope someone finds this useful.
The UMFT602A Example was designed for a Cyclone V GX Starter Kit, but all I had in my office was a DE2-115 with a Cyclone IV FPGA. I've ported the code to the DE2. Here are the steps I've followed:
1 - Leave the UMFT602A jumpers and configuration untouched: 2.5 V, FT600 protocol. etc;
2 - Change the DE2 board IO Voltages using the respective jumpers. Mine was configured to 3V3 so I changed it to 2V5;
3 - Connect the FT602 module to the FPGA board with the HSMC connector, then use a USB 3.0 cable to connect the module and the PC. The USB 2.0 cable didn't work for me;
4 - In the Quartus example, upgrade the IPs and change everything in the project to Cyclone IV E;
5 - The PLL used in the Cyclone V FPGA is not compatible with Cyclone IV ones. I had to change the IP and use 2 Cyclone IV PLLs in order to achieve the same outputs. I had to add a second clock input pin as well so that the synthesizer wouldn't give me timing warnings;
6 - In Quartus, edit the .qsf file to change the pinout. Check the "DE2-115 User Manual" and the "Cyclone V GX Starter Kit User Manual" to do that;
Related Documents:
FTDI:
- AN_434 FT602_UVC_Bus_Master_Sample
- AN_435 FT602 UVC Chip Configuration Guide
- AN_377 Altera FPGA FIFO master Programming Guide
Altera/Intel:
- DE2-115 User Manual
- Cyclone V GX Starter Kit User Manual
- Cyclone IV Device Handbook, Volume 1 (For the PLLs)
- Other docs about Altera's IPs like "altera_pll" (Cyclone V) and "ALTPLL" (Cyclone IV)