Hi,

if you compile the file below the same way as in my previous post:

/*********************************************************************************
*********************************************************************************/

rom unsigned char DevsDefs[] =
{
   0x08, 0x10, 0x00, 0x01, 0x00, 0xe6,
};

unsigned short vID;
unsigned long idx;

/*********************************************************************************
*********************************************************************************/

void main(void)
{
   for (;; );
}

/********************************************************************************/
/********************************************************************************/

void cmd_def()
{
   vID = (DevsDefs[idx++] << 8 ) | DevsDefs[idx++];
}

/********************************************************************************/
/********************************************************************************/

it will produce this incorrect code between the 0x00440 and 0x0048a addresses:

003c0 fa00 03e0           JUMP 0x003e0
003c2 fa00 03c0           JUMP 0x003c0
003c4 fa00 03be           JUMP 0x003be
003c6 fa00 03c0           JUMP 0x003c0
003c8 fa00 03c0           JUMP 0x003c0
003ca fa00 03c0           JUMP 0x003c0
003cc fa00 03c0           JUMP 0x003c0
003ce fa00 03c0           JUMP 0x003c0
003d0 de00 0000 0000 0000 CMP32 0x0000 $0x00000000
003d4 0000                NOP
003d5 0000                NOP
003d6 0000                NOP
003d7 0000                NOP
003d8 2e78               
003d9 7a79               
003da 0000                NOP
003db 0000                NOP
003dc 0000                NOP
003dd 0000                NOP
003de 0000                NOP
003df 0000                NOP
003e0 b028 0001           OUTPORT 0x028 $0x01
003e2 bc00 3ffc           INPORT 0x000 0x3ffc
003e4 3204 3ffc           SHR8 0x3ffc $0x04
003e6 da01 3ffc           CMP8 0x3ffc $0x01
003e8 fa40 0408           JNZ 0x00408
003ea b00f 0000           OUTPORT 0x00f $0x00
003ec b080 0012           OUTPORT 0x080 $0x12
003ee b088 000f           OUTPORT 0x088 $0x0f
003f0 b089 00f0           OUTPORT 0x089 $0xf0
003f2 b084 0000           OUTPORT 0x084 $0x00
003f4 b085 0000           OUTPORT 0x085 $0x00
003f6 b08a 00ff           OUTPORT 0x08a $0xff
003f8 b08b 003f           OUTPORT 0x08b $0x3f
003fa b081 0001           OUTPORT 0x081 $0x01
003fc c883 0000           PORTTST 0x083 $0 Z
003fe fa40 03fc           JNZ 0x003fc
00400 b080 0000           OUTPORT 0x080 $0x00
00402 b088 0000           OUTPORT 0x088 $0x00
00404 b089 0000           OUTPORT 0x089 $0x00
00406 b083 00ff           OUTPORT 0x083 $0xff
00408 2600 3ffa 0916 0000 LD32 0x3ffa $0x00000916
0040c 3201 bffa           SHR32 0x3ffa $0x01
0040e 2400 3ffe 0000      LD16 0x3ffe $0x0000
00411 2400 3ff8 001e      LD16 0x3ff8 $0x001e
00414 3201 7ff8           SHR16 0x3ff8 $0x01
00416 dc00 3ff8 0000      CMP16 0x3ff8 $0x0000
00419 fa1c 042a           JLE 0x0042a
0041b 2d01 3ffa 3ffe      CPYROM (0x3ffe) 0x3ffa $01
0041e 6c00 3ffe 0002      ADD16 0x3ffe $0x0002
00421 6e00 3ffa 0001 0000 ADD32 0x3ffa $0x00000001
00425 6c20 3ff8 0001      SUB16 0x3ff8 $0x0001
00428 fa00 0416           JUMP 0x00416
0042a 2600 3ffc 0000 0000 LD32 0x3ffc $0x00000000
0042e 2600 3ff8 0000 0000 LD32 0x3ff8 $0x00000000
00432 0a00 0000           SP_LOAD $0x0000
00434 fa00 043d           JUMP 0x0043d
00436 0000                NOP
00437 0000                NOP
00438 0000                NOP
00439 0000                NOP
0043a 1008               
0043b 0100                CPYF Z Z
0043c e600               
0043d fa00 043d           JUMP 0x0043d
0043f 0006                RTS
00440 f200 800c           PUSH32 0x000c
00442 f200 8010           PUSH32 0x0010
00444 2600 0004 0001 0000 LD32 0x0004 $0x00000001
00448 3e00 8004 0020 000c SHR32 0x000c 0x0020 0x0004
0044c 2600 0010 043a 0000 LD32 0x0010 $0x0000043a
00450 7400 8010 000c      ADD32 0x000c 0x0010
00453 2c01 000c 0000      CPYROM 0x0000 0x000c $01
00456 fa52 045a           JNF1 0x0045a
00458 3208 4000           SHR16 0x0000 $0x08
0045a 4400 0000 0010      CPY8 0x0010 0x0000
0045d 4400 0010 0000      CPY8 0x0000 0x0010
00460 4e00 0000 00ff 0000 AND32 0x0000 $0x000000ff
00464 2600 0004 0008 0000 LD32 0x0004 $0x00000008
00468 3e20 8004 0000 0010 SHL32 0x0010 0x0000 0x0004
0046c 2c01 000c 0000      CPYROM 0x0000 0x000c $01
0046f fa52 0473           JNF1 0x00473
00471 3208 4000           SHR16 0x0000 $0x08
00473 4400 0000 000c      CPY8 0x000c 0x0000
00476 4e00 000c 00ff 0000 AND32 0x000c $0x000000ff
0047a 5440 8010 000c      OR32 0x000c 0x0010
0047d 8201 8020           INC32 0x0020 $0x01
0047f 8201 8020           INC32 0x0020 $0x01
00481 8201 8020           INC32 0x0020 $0x01
00483 4400 400c 001e      CPY16 0x001e 0x000c
00486 f380 0010           POP32 0x0010
00488 f380 000c           POP32 0x000c
0048a 0006                RTS
0048b 0000                NOP
0048c 0000                NOP
0048d 0000                NOP
0048e 0000                NOP
0048f 0000                NOP
00490 0000                NOP
00491 0000                NOP
00492 0000                NOP
00493 0000                NOP
00494 0000                NOP
00495 0000                NOP
00496 0000                NOP
00497 0000                NOP
00498 0000                NOP
00499 0000                NOP
0049a 1808               
0049b 150f               
0049c 2438 e4d7 0025      LD16 0x24d7 $0x0025

The idx variable is incremented by 3 instead of 2.
The second jnf1 instruction should be jf1 and it lack of a second shr32 instruction.


Willy.

Hi

I wasted my time to try to found why my code is not working properly and the reason seems to be your VinAsm tool.

Look at this piece of my code:

...

typedef struct _BSS_t
{

   ...
   unsigned char devsState;
   ...

} BSS_t;

...

BSS_t *BSS;

...

unsigned char msk1;
unsigned char msk2;
unsigned char msk3;
unsigned char msk4;
unsigned char msks1;
unsigned char msks2;

...

void cmd_cr()
{
   msk1 = HOST_DD1;
   msk2 = HOST_DD2;
   msk3 = HOST_DR1;
   msk4 = HOST_DR2;

   msks1 = (HOST_DD1 | HOST_DD2 | HOST_DR1 | HOST_DR2);
   msks2 = ~(HOST_DD1 | HOST_DD2 | HOST_DR1 | HOST_DR2);

   BSS->devsState &= ~(HOST_DD1 | HOST_DD2 | HOST_DR1 | HOST_DR2);
}

...

The compilation process produce a code which seems correct to me in the ".asm" generated file:

.FUNCTION   "cmd_cr"   

.RETURN "void"   0   0   0   3   0   0   0   
PUSH32   %r0
PUSH32   %r1
.LINE   56
LD8   msk1   $1
.LINE   57
LD8   msk2   $2
.LINE   58
LD8   msk3   $4
.LINE   59
LD8   msk4   $8
.LINE   61
LD8   msks1   $15
.LINE   62
LD8   msks2   $240
.LINE   64
LD16   %r0   $BSS
CPY16   %r0   (%r0)
LD16   %ebx   $280
ADD16   %r0   %ebx
CPY8   %r1   (%r0)
AND8   %r1   $240 <-----
CPY8   (%r0)   %r1
.LINE   64
POP32   %r1
POP32   %r0
RTS   
.FUNC_END   "cmd_cr"

Look especially at the marked line: $240 = 0xf0 which is effectively ~(HOST_DD1 | HOST_DD2 | HOST_DR1 | HOST_DR2)

But when i take a look at the disassembler file genereted during debugging, i find this which explain why my code doesn't work:

158ee f200 800c           PUSH32 0x000c
158f0 f200 8010           PUSH32 0x0010
158f2 2201 03af           LD8 0x03af $0x01
158f4 2202 03b0           LD8 0x03b0 $0x02
158f6 2204 03b1           LD8 0x03b1 $0x04
158f8 2208 03b2           LD8 0x03b2 $0x08
158fa 220f 03b3           LD8 0x03b3 $0x0f
158fc 22f0 03b4           LD8 0x03b4 $0xf0
158fe 2400 000c 03ad      LD16 0x000c $0x03ad
15901 4401 400c 000c      CPY16 0x000c (0x000c)
15904 2400 0004 0118      LD16 0x0004 $0x0118
15907 7400 4004 000c      ADD16 0x000c 0x0004
1590a 4401 000c 0010      CPY8 0x0010 (0x000c)
1590d 4a30 0010           AND8 0x0010 $0x30 <-----
1590f 4500 0010 000c      CPY8 (0x000c) 0x0010
15912 f380 0010           POP32 0x0010
15914 f380 000c           POP32 0x000c
15916 0006                RTS

0x03ad is the address of the BSS pointer. 0x118 is the offset of the devsState member in the BSS_t structure.

Look especially at the marked line: 0x30 is not 0xf0 and then is not ~(HOST_DD1 | HOST_DD2 | HOST_DR1 | HOST_DR2) !

Is this a known bug ?

Apparently, this is a problem with the &= operator: If i replace

BSS->devsState &= ~(HOST_DD1 | HOST_DD2 | HOST_DR1 | HOST_DR2);

by

BSS->devsState = BSS->devsState & ~(HOST_DD1 | HOST_DD2 | HOST_DR1 | HOST_DR2);

i obtain this code:

15951 2400 0014 03ad      LD16 0x0014 $0x03ad
15954 4401 4014 0018      CPY16 0x0018 (0x0014)
15957 2400 0004 0118      LD16 0x0004 $0x0118
1595a 7400 4004 0018      ADD16 0x0018 0x0004
1595d 4401 4014 0014      CPY16 0x0014 (0x0014)
15960 2400 0004 0118      LD16 0x0004 $0x0118
15963 7400 4004 0014      ADD16 0x0014 0x0004
15966 4401 0014 0014      CPY8 0x0014 (0x0014)
15969 4400 0014 0000      CPY8 0x0000 0x0014
1596c 4e00 0000 00ff 0000 AND32 0x0000 $0x000000ff
15970 2600 0014 fff0 ffff LD32 0x0014 $0xfffffff0
15974 5400 8000 0014      AND32 0x0014 0x0000
15977 4500 0014 0018      CPY8 (0x0018) 0x0014

which works but is badly optimized.

Willy.

Hi,

thank you for your reply. My confusion came from the "i2c.h" file which talk about pin number starting at one.

Things go better now as there is activity on clock and data signals, but it doesn't work yet. Look at this source code:

   #define VOS_DEV_I2C 5

   // Configure direction of port B
    vos_gpio_set_port_mode(GPIO_PORT_B, 0x0c);

    // i2c interface
    vos_iomux_define_output(14, IOMUX_OUT_GPIO_PORT_B_2);
    vos_iomux_define_output(15, IOMUX_OUT_GPIO_PORT_B_3);

    // Needed declarations
    i2c_ioctl_cb_t i2c_iocb;
    i2c_port_t i2c_port;
    unsigned char i2cerr;

    char i2c_Buf[8];
    uint16 i2c_Nbr;

    VOS_HANDLE hI2C;

    // Define the I2C pins
    i2c_port.clkPort = I2C_PORT_B;
    i2c_port.clkPortNo = 3; // Pin 15
    i2c_port.dataPort = I2C_PORT_B;
    i2c_port.dataPortNo = 2; // Pin 14
    i2cerr = i2c_device_init(VOS_DEV_I2C, &i2c_port);

    // Open I2C Interface
    hI2C = vos_dev_open(VOS_DEV_I2C);

    // Set RTC address
    i2c_iocb.ioctl_code = VOS_IOCTL_I2C_SET_DEVICE_ADDRESS;
    i2c_iocb.data = 0x68;
    i2cerr = vos_dev_ioctl(hI2C, &i2c_iocb);

    // Set I2C options
    i2c_iocb.ioctl_code = VOS_IOCTL_I2C_SET_OPTIONS;
    i2c_iocb.data = I2C_OPTIONS_READ_ADDRESS;
    i2cerr = vos_dev_ioctl(hI2C, &i2c_iocb);

    // Set address to read
    i2c_iocb.ioctl_code = VOS_IOCTL_I2C_SET_RDWR_ADDRESS;
    i2c_iocb.data = 0x00;
    i2cerr = vos_dev_ioctl(hI2C, &i2c_iocb);

    // Read one byte form Addess 0x00
    i2cerr = vos_dev_read(hI2C, i2c_Buf, 1, &i2c_Nbr);

First: All vos_dev_ioctl() calls return 1. From what i saw in the disassembly code window, this is normal and each call successfully did its job. But according to the manual, the vos_dev_ioctl() function should return 0 in case of success.

Second: The vos_dev_read() fail and return 2. With my scope, i know that the first byte (which contain the start condition,the chip address, the direction bit) is sent to the RTC which response with an ACK. But that is all i see and the R/W bit is set to 0 instead of 1 for a read.

I tried to find where the problem could be in the assembler code, but your debugger doesn't allow to put breakpoint in the assembler code which makes the debug process almost impossible.

Maybe, i do something wrong, but i don't know what.

In attachment, you will find the result of the vos_dev_read() function.

Can you help me again ?

Thanks.