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Topics - bhoomil

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I have a requirement like,
Send FPGA specific cmd (i.e. set/get register, download firmware etc. ) to send from host to FPGA via FT601. I found that FT_ControlTransfer() API can do this thing by setting up the tSetupPacket field. But I have one query, How such vendor-specific request handle by FT601 core. Does EP0 data comes out to slave FIFO and send it to the master FIFO of FPGA just like in case of IN/OUT EP?

Bhoomil C.

Hi All,
Currently, my team is working on design steps for data acquisition system which will ultimately control by PC/host. We are choosing USB3.0 line between our DAQ board/DEVICE and PC/HOST. Custom code for reading data from ADC and writing to control register is inside FPGA.
To communicate with FPGA over USB we came across one smart solution from FTDI called FT601 USB3.0 to FIFO bridge.

After reading data sheets and FT_xyz APIs from d3xx libs, our team could understand How to communicate with FT601 bridge and how we can control FIFO master and FPGA.

Now main questions to FTDI technical panel is that,
1) does d3xx driver/lib are using DMA fundamental?
2) does d3xx source are available for the selected developer?
3) what if (our actual requirement) I want to save data stream comes from the IN EP from DAQ board and save directly it into the pre-allocated DMA buffer? Could Such things be possible with d3xx driver/lib? I want to do this because I need max throughput and min CPU util. during large buffer transfer operation.

Note: hosts will be both Linux and/or Windows 7+ OS.

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