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Discussion - Hardware / Re: About the input delay of FPGA when connecting FT601 with FPGA
« on: February 08, 2021, 09:33:45 PM »
Here's what the example application suggests for Quartus:
Here's what I used for Xilinx 7-series in Vivado, which I believe is correct:
The FT601->FPGA figures (set_input_delay) are easy to meet either way.
The FPGA->FT601 figures (set_output_deay) are practically impossible to meet because of the very long hold requirement. Of course, if you use "hold" instead of "minus hold" for set_output_delay -min (as in the example application) the timing analysis will succeed every time.
Code: [Select]
set_input_delay -clock [get_clocks fifoClk] -max 7 [get_ports {BE[*] DATA[*]}]
set_input_delay -clock [get_clocks fifoClk] -min 6.5 [get_ports {BE[*] DATA[*]}]
set_output_delay -clock [get_clocks fifoClk] -max 1.0 [get_ports {BE[*] DATA[*]}]
set_output_delay -clock [get_clocks fifoClk] -min 4.8 [get_ports {BE[*] DATA[*]}]Here's what I used for Xilinx 7-series in Vivado, which I believe is correct:
Code: [Select]
# max delay is 7.0 (from FTDI docs) + 0.4 data wires - 0.2 clock wire = 7.2
set_input_delay -clock [get_clocks clk_ftdi] -max 7.2 [get_ports {ftdi_data_*}]
# min delay is 3.5 (from FTDI docs) + 0.2 data wires - 0.2 clock wire = 3.5
set_input_delay -clock [get_clocks clk_ftdi] -min 3.5 [get_ports {ftdi_data_*}]
# max delay is 1.0 (from FTDI docs) + 0.4 data wires + 0.2 clock wire = 1.6
set_output_delay -clock [get_clocks clk_ftdi] -max 1.6 [get_ports {ftdi_data_*}]
# min delay is -4.8 (from FTDI docs) + 0.2 data wires + 0.2 clock wire = -4.4
set_output_delay -clock [get_clocks clk_ftdi] -min -4.4 [get_ports {ftdi_data_*}]The FT601->FPGA figures (set_input_delay) are easy to meet either way.
The FPGA->FT601 figures (set_output_deay) are practically impossible to meet because of the very long hold requirement. Of course, if you use "hold" instead of "minus hold" for set_output_delay -min (as in the example application) the timing analysis will succeed every time.