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Messages - cioma

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1
General Discussion / Re: Programming Altera Cyclone II using FT232H
« on: January 09, 2021, 11:11:56 AM »
Try UrJTAG

2
Discussion - Hardware / Re: Programming Altera Cyclone II using FT232H
« on: January 09, 2021, 11:08:02 AM »
Try UrJTAG

3
Discussion - Hardware / Re: FT230XS
« on: January 09, 2021, 10:37:59 AM »
It's a known phenomenon in electronics: unpowered chip gets powered trough its internal ESD protection diodes when its signals are driven high.
The right way to deal with it is to use buffers with so-called Ioff feature (e.g. TI SN74AUP1G34) or a dual-supply voltage translators (e.g. ON FXMA2102).
Using series high-value resistors is not ideal as it will make signal edges very slow.

4
Discussion - Hardware / Re: Future of FT232H, FT2232H, FT4232H?
« on: November 24, 2020, 11:27:36 AM »
Thanks for the information.

But what I really interested in is MPSSE engine so FT4222H is not suitable for my needs as I need JTAG, I2C, SPI, Microwire, MDIO interfaces.

5
Discussion - Hardware / Future of FT232H, FT2232H, FT4232H?
« on: October 24, 2020, 12:02:11 PM »
Could FTDI please let us know if they are going to release new devices similar to FT232H, FT2232H, FT4232H in the future?

My ideal devices would be:

- High-speed USB
- 1, 2, 4, 8 channel device variants
- UART, MPSSE, bit bang on every channel
- xDBUS[7:0] ports only, no need for xCBUS[7:0] ports
- At least 8 kByte RX FIFO buffer and 8 kByte TX FIFO buffer for each channel
- At least 100 MHz internal clock (vs the current 60 MHz)
- Each port pin shall be independently configurable as open-drain
- Support for all SPI modes
- Support for I2C clock stretching
- Support for I2C multi-master
- Small QFN package with 0.5 mm pin pitch

6
Discussion - Drivers / FT60x protocol documentation
« on: September 21, 2020, 12:22:04 PM »
Assuming FTDI is interested in selling more chips it would be great if they opened their FT60x protocol documentation (and the same for other chips too).
We know we can use FTDI drivers but many of us would like to write clean code in selected language using generic libraries (e.g. libusb).
Just a thought :)

7
Discussion - Hardware / Re: FT4232H_I2C connection
« on: September 03, 2020, 05:27:04 PM »
Pinouts for FT232H, FT2232H, FT4232H MPSSE

Pin        JTAG  SPI   I2C
D0, output TCK   SCK   SCL
D1, output TDI   MOSI  SDAO
D2, input  TDO   MISO  SDAI
D3, output TMS   SS#   no connection

8
If my FT231X CBUS[0:3] pins are configured as "GPIO" in MTP can I control them (configure as input or output, write and read pin values) from Java D2xx library for Android?

9
Did you configure FT230X as self-powered device using FT_Prog?

10
Discussion - Software / Re: FT_Prog on Windows 10
« on: April 23, 2019, 09:18:27 AM »
My 5p:

The latest FT_Prog messes up LG 27MD5KA-B Thunderbolt display backlight settings on Windows 10 when it scans for FTDI devices: screen backlight blinks every 0.5s during scan and ends up being very dim (one can hardly see anything on it). The workaround is to start the scan again and unplug the display from PC during it. After replugging it might end up with the original backlight settings.

11
Discussion - Software / Re: Understanding FT232H buffer behavior
« on: April 23, 2019, 09:05:03 AM »
AFAIK the USB bulk transfers (512 bytes packets in High Speed mode) are used for actual data exchange. Any amount of data may be sent to OUT endpoint as USB subsystem on the host computer handles this automatically: device sends NAK on the OUT endpoint when its buffer gets full and the host computer reschedules the data delivery. Therefore there is no need to split write data in 512 byte chunks. And the data is buffered on the host computer. Same for the IN endpoint: host computer buffers data until either its size reaches the limit you've requested (e.g. 64 kB) or a timeout occurs.

12
Discussion - Hardware / Re: SPI mode clock duty cycle
« on: January 09, 2018, 11:54:34 AM »
Do you by any chance have 3-phase clocking enabled?

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