Hi Tony,

Your only option would be to add some external pulldown on the GPIOH pins. Even if they have been set as low and input, if there is no connection they will be pulled high by the internal pullups.

Best Regards
FTDI Community

Hello,

When using LibMPSSE, GPIOL[0:3] can only be used as SPI chip selects.
 
When using LibMPSSE, there is no way to control GPIOL[0:3] as GPIO.
 
LibMPSSE demonstrates controlling the higher line bytes (GPIOH) while using SPI on the lower line bytes using the following functions:
 
FT_WriteGPIO
FT_ReadGPIO
 
If you want to control some of the unused lower line bytes on the same ADBUS as SPI then see AN_411 FTx232H MPSSE I2C Master Example in C which demonstrates GPIO usage with MPSSE using D2xx direct (not using LibMPSSE).
This could be used as a base to understand using both SPI/GPIO in the same code.
OK this example is for I2C but the same principles apply to SPI.

Best Regards
FTDI Community

Hello,

Unfortunately the LibFT4222 source code can't be shared as it's exposes secrets of our vendor class devices.

Please contact us via email on support1@ftdichip.com and we'll contact our R&D team to see if we can provide a 64 Bit (aarch64) build.

Best Regards,
FTDI Community

Hello,

Yes, there are internal pullups on the RXD lines of FT232R and FT232H.

the typical value is 75 KΩ. You can find more information in 5.3 of the FT232H datasheet.

Best Regards
FTDI Community

Hi,

Have a look at section 3.2 of AN_412 FT600/FT601 Bridge Chips Integration, this goes over the abort recovery process.

Any error or timeout requires this abort process before resuming the read/write.

Best Regards
FTDI Community

Hi,

We don't have any references for doing SPI communication using Bit-Bang. I would recommend that you use the MPSSE for SPI communication instead.   

To use I2C/SPI as a master (no slave functionality), see AN_135 MPSSE Basics and our existing MPSSE Example projects:
 
MPSSE Examples
 
There are two options to use I2C/SPI modes with the MPSSE engine:
 
a.   Use LibMPSSE libraries. Example code is provided with the download. Source code is also provided.
b.   Use D2XX drivers direct. Example code is shown at I2C / SPI. AN_108 Command Processor For MPSSE and MCU Host Bus Emulation Modes provides the necessary information.
 
Option b is the best option to use the D2XX drivers direct (no dependency on libMPSSE library).

Also please also note, SPI modes 1 and 3 are not supported with our MPSSE engine.
So please check that your SPI device doesn’t work with these modes.

You can find all the referenced documentation above, here

Hi,

yes, FT2232H is a high-speed device. The driver can only operate with 1ms latency minimum.

Best regards
FTDI Community

Hello,

There are 2 kinds of delays / pauses.

1. Occurs when FIFO switches from ping to pong buffer. There are 2 FIFO Buffers and when current one gets filled, hardware moves to second FIFO. There will be a brief delay during this period.
2. Occurs when a session is ended and a new session is created. This delay can be slightly larger than the above one.
A session will be ended when the length of transferred data equals with the stream length set by FT_SetStreamPipe API (if not in stream mode, then the length passed in Read Pipe API), or when an unaligned write happens.
 
Between the end of session and start of new session, there could be some delay as observed.

If the stream length is shorter, this delay will be seen often.
The recommended stream length is, several multiples of the FIFO size.
For example, if the FT600 configuration uses 4K FIFO size, it's best to make the stream length as multiples of 4K - Say 10 times or 100 times of 4K.
This way, instead of seeing a long delay every 4K, the long delay will happen only at 400K transfer boundaries.

The FPGA is expected to buffer at least a FIFO size worth of data so that the delay does not cause any issues such as overflow.

If you have any additional questions please contact us via email as we have already been in contact with you.

Best Regards,
FTDI Community