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 1 
 on: Today at 04:17:53 PM 
Started by a4711 - Last Post by FTDI Community
Hello,

Unfortunately the LibFT4222 source code can't be shared as it's exposes secrets of our vendor class devices.

Please contact us via email on support1@ftdichip.com and we'll contact our R&D team to see if we can provide a 64 Bit (aarch64) build.

Best Regards,
FTDI Community

 2 
 on: March 27, 2024, 08:58:33 PM 
Started by a4711 - Last Post by a4711
It is becoming more and more common to install a 64 Bit OS on a Raspberry. Libft4222 is available for ARMv8 32 Bit architecture, but not for 64 Bit (aarch64). When will you publish it or when will you publish the source code of LibFT4222 so that we can compile it on any architecture?

Thanks.

 3 
 on: March 26, 2024, 12:39:15 PM 
Started by hari - Last Post by hari
I have a custom made board and it has FTDI 2232H chip for serial data transfer. So to start with very basic steps, I assigned the usb data pins to LEDS to vies the output that I send over the serial communication port.

 

following is my very basic verilog code to check the working of USB,

The board has differential clock each working at 25MHZ. So the board is made to work at 50MHZ frequency as implemented in the following code,

Code: [Select]
module transfer(
input [7:0] usb_d,
input usb_rxfn, input usb_txen,
output usb_rdn, output usb_wr,
input CLK_IN_P,  input CLK_IN_N,  output reg [7:0] led);
   
wire CLK_IN;
 
IBUFDS IBUFDS_CLKIN (.I(CLK_IN_P), .IB(CLK_IN_N), .O(CLK_IN));
 wire clkin;
  assign clkin = CLK_IN;
 
 
reg [7:0]a;
 
always@(posedge clkin)
 
begin
 a[0]=usb_d[0] &1;
 a[1]=usb_d[1] &1;
 a[2]=usb_d[2] &1;
 a[3]=usb_d[3] &1;
 a[4]=usb_d[4] ^1;
 a[5]=usb_d[5] ^1;
 a[6]=usb_d[6] ^1;
 a[7]=usb_d[7] ^1;
 
 
 led[0]=a[0];
 led[1]=a[1];
 led[2]=a[2];
 led[3]=a[3];
 led[4]=a[4];
 led[5]=a[5];
 led[6]=a[6];
 led[7]=a[7];
 end
 
endmodule

Also, the thing I observed is, when the bit file is programmed, the leds[4] to leds[7] start blinking, which denotes that before even the values arrive from usb_d[4] to usb_d[7] the default values it assumes is '0'.

Following is the constraint file used

Code: [Select]
set_property IOSTANDARD LVCMOS33 [get_ports usb_rdn]
set_property IOSTANDARD LVDS_25 [get_ports CLK_IN_P]
set_property IOSTANDARD LVDS_25 [get_ports CLK_IN_N]
set_property IOSTANDARD LVCMOS33 [get_ports usb_wr]
set_property IOSTANDARD LVCMOS33 [get_ports usb_txen]
 
set_property IOSTANDARD LVCMOS33 [get_ports usb_rxfn]
set_property PACKAGE_PIN F1 [get_ports usb_rxfn]
set_property PACKAGE_PIN E1 [get_ports usb_rdn]
 
set_property PACKAGE_PIN E2 [get_ports usb_txen]
set_property PACKAGE_PIN D2 [get_ports usb_wr]
set_property PACKAGE_PIN E3 [get_ports CLK_IN_P]
 
create_clock -period 20.000 -name CLK_IN [get_ports CLK_IN_P];
 
set_property PACKAGE_PIN R12 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN T11 [get_ports {led[6]}]
set_property PACKAGE_PIN T9 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U11 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN V11 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V10 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN R10 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN T10 [get_ports {led[0]}]
set_property PACKAGE_PIN J3 [get_ports {usb_d[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {usb_d[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {usb_d[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {usb_d[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {usb_d[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {usb_d[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {usb_d[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {usb_d[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {usb_d[6]}]
set_property PACKAGE_PIN H4 [get_ports {usb_d[6]}]
set_property PACKAGE_PIN G4 [get_ports {usb_d[5]}]
set_property PACKAGE_PIN G3 [get_ports {usb_d[4]}]
set_property PACKAGE_PIN H2 [get_ports {usb_d[3]}]
set_property PACKAGE_PIN H1 [get_ports {usb_d[2]}]
set_property PACKAGE_PIN G2 [get_ports {usb_d[1]}]
set_property PACKAGE_PIN G1 [get_ports {usb_d[0]}]

I used serial command to send data from matlab, following is my complete code in Matlab

Code: [Select]
s=serail('COM27');
fopen(s);
d=['01'];
d1=sscanf(d,'%d');
fwrite(s,d1,'uint8');
fclose(s);

 4 
 on: March 21, 2024, 03:32:52 PM 
Started by mnecetinkaya - Last Post by FTDI Community
Hello,

The extra bytes may be due to lack of biasing on the RS485 transceiver. If you could email into support1@ftdichip.com we can share the RS485 biasing schematic that will be able to help you.

Best Regards
FTDI Community 

 5 
 on: March 21, 2024, 01:18:18 PM 
Started by mnecetinkaya - Last Post by mnecetinkaya
Hi everyone,

I have a problem like I mention in title shortly. I designed a board to communicate between pc and a device which use RS485. I can communicate but every time receive a data it comes with a FE or FF byte as prefix. I'm using FT2232HQ with ADM3485EARZ-REEL7 on my board. Then I used USB-COM485-PLUS2 and I compared the waveform of the two converters. Even though the waveforms are same, I did not receive any extra byte while using USB-COM485-PLUS2. I wonder if I get schematic of COM485-PLUS2? Or does anyone have an idea about that situation?

 6 
 on: March 21, 2024, 12:21:42 PM 
Started by brumbarchris - Last Post by brumbarchris
Thank you.

Cristian

 7 
 on: March 21, 2024, 10:48:38 AM 
Started by brumbarchris - Last Post by FTDI Community
Hello,

Yes, there are internal pullups on the RXD lines of FT232R and FT232H.

the typical value is 75 KΩ. You can find more information in 5.3 of the FT232H datasheet.

Best Regards
FTDI Community

 8 
 on: March 20, 2024, 05:01:36 PM 
Started by brumbarchris - Last Post by brumbarchris
Hello,
I have two FTDI cables based on the FT232H (a C232HMDDHSL-0 and a C232HD-DDHSP-0) and one based on the FT232R (TTL-232R-3V3).

In active mode (device enumerated after EEPROM read) the RXD pin is HIGH on these devices (some 2.5V on the FT232H based cables and 3.3V on the FT232R based cable). Now, in this mode, this pin operates as an input. In order to be high, it must have a pull-up. Is there any information available with regards to this pull-up (its value)?

The datasheet of the FT232R might infer the presence of a 200k pull-up on this pin, with this statement which is present after Table 5.10:
Quote
** Only input pins have an internal 200KΩ pull-up resistor to VCCIO

But there is nothing on this in the FT232H datasheet (although it talks about pull-ups on various other pins, the RXD pin is not mentioned).

I am familiar also with AN_184 FTDI Device Input Output Pin States, but that didn't help either, it just indicates that in in active mode the RXD pin is configured as "Function".

Regards,
Cristian

 9 
 on: March 14, 2024, 10:52:13 AM 
Started by Arsen - Last Post by FTDI Community
Hi,

Number 1 is just the general configuration of the device. Number 2 is to enable the GPIOs. Have a look at section 3.1 of AN_412 FT600/FT601 Bridge Chips Integration.

This goes over the configuration modes of FT600 with section 3.1.5 focusing on the GPIO configuration.

We have a FT60x configuration programmer that you can use. You can find it here along with the AN_370 FT60X Configuration Programmer User Guide.

Best Regards
FTDI Community

 10 
 on: March 14, 2024, 10:14:56 AM 
Started by Arsen - Last Post by Arsen
Thank you very much for Your reply.

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