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Author Topic: FT601 FIFO Bus AC Timing and FPGA constraints in AN_421  (Read 1115 times)

ilya79

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FT601 FIFO Bus AC Timing and FPGA constraints in AN_421
« on: August 16, 2018, 10:50:31 AM »

Hi!  FT601datasheet (table 4.2 FIFO Bus AC timing) points that in worst case slave drive sata set up time is 3 ns. In AN_421 document (FIFO Bus Master for FT60x application note) on page 19, in timing constraints this parameter is set to 6 ns (TIMEGRP "M_FIFO_IO" OFFSET = IN 6 ns VALID 6.5 ns BEFORE "CLK" RISING).  What value is correct ?     
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Re: FT601 FIFO Bus AC Timing and FPGA constraints in AN_421
« Reply #1 on: August 17, 2018, 01:29:31 PM »

Hello,

Please can you contact email support on support1@ftdichip.com and we will look into this, the outcome of which we will post here.

Regards,
FTDI Community
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