General Category > Discussion - Drivers

issue related to UM232H eval. board

<< < (3/3)

FTDI Community:
Hello,

The signal may be degraded by rounding of edges and lowering of apparent amplitude if you have long connections or due to your scope probe. We recommend to use a high-frequency low-capacitance probe to measure the signal to ensure that what is shown on the scope is correct and that the probe itself does not affect the waveform by adding capacitance.

Some probes also have different characteristics depending on which mode they are in (e.g. 1x vs 10x). The probe used should have a frequency rating several times greater than the signal being measured and so generally a 200MHz or 300MHz probe is needed to see this signal accurately. Please check the datasheet of your probe to ensure that the 60MHz is well within its range.

Best Regards, FTDI Community

Rajesh@sys:
thanks for the previous suggestions


As i indicated earlier,

we are using  FPGA based hardware to write the data in UM232H(tool ISE). After some no of writes TXE is gone low to high, Hence, we are NOT able write further.
our understanding is that , Sense the visual studio/laptop  does NOT do fifo read operation. The TXE remains high,
our current issue is
 we are not able to read back the data from UM232h/FIFO via COM PORT. because we are using synchronous fifo mode(using ONLY D2XX).


<
FYI
so for configuring UM232H in synch. fifo mode and reading we are using VISUAL STUDIO 2017.>


i want to know


1)how does visual studio knows when to read the data from fifo.
                is it based on any bit of the software register (or) any hardware signal from board. (such as fifo full)—it is not accessible by the software

3)how to access read operation from visual studio.

FTDI Community:
Hello,

Yes, TxE# tells your FPGA that there is space in the buffer and if you keep writing data to the FIFO without reading at the PC side, then the buffer will fill up and the device will tell you to stop.

Your application in Visual Studio should check for data being available using FT_GetStatus or FT_GetQueueStatus as shown in the document below. If there is any data available (RxBytes > 0) then you would read the data with FT_Read.

When you write the data to the FIFO from the FPGA, you will find that FT_GetStatus/FT_GetQueueStatus show the number of bytes. You can use a loop in the application in Visual Studio which keeps checking for data and reads any data available and puts it in a buffer in the application.

You can find the example code in the document below.

https://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_167_FIFO_Basics.pdf

Best Regards, FTDI Community

Navigation

[0] Message Index

[*] Previous page

Go to full version