FTDI Community

Please login or register.

Login with username, password and session length.
Advanced Search  

News:

Welcome to the FTDI Community!

Please read our Welcome Note

Technical Support enquires
please contact the team
@ FTDI Support


New Bridgetek Community is now open

Please note that we have created the Bridgetek Community to discuss all Bridgetek products e.g. EVE, MCU.

Please follow this link and create a new user account to get started.

Bridgetek Community

Author Topic: FT601 - 66MHz FIFO clock  (Read 9391 times)

vytautasb

  • Newbie
  • *
  • Posts: 3
    • View Profile
FT601 - 66MHz FIFO clock
« on: June 11, 2019, 07:56:34 AM »

Hi,

i am having difficulties running FT601 with 66MHz FIFO clock setting in Multi-Channel FIFO mode. We are using our custom board and example design for Altera FPGA.

I am using timing constraints provided in example design and example runs fine with 100MHz FIFO clock, but when i change FIFO clock setting (in configuration utility) to 66MHz example design does not work. I have tried editing timing constraints file for FPGA and change clock period from 100Mhz to 66 MHz but this does not help. 

Is there anything else has to be changed to make example design work with 66Mhz FIFO clock?
Logged

FTDI Community

  • Administrator
  • Hero Member
  • *****
  • Posts: 892
    • View Profile
Re: FT601 - 66MHz FIFO clock
« Reply #1 on: June 11, 2019, 09:19:40 AM »

Hello,

I see that you have also contacted email support where we will deal with your issue and post an outcome here.

Regards,
FTDI Community
Logged

vytautasb

  • Newbie
  • *
  • Posts: 3
    • View Profile
Re: FT601 - 66MHz FIFO clock
« Reply #2 on: June 11, 2019, 09:22:26 AM »

Hello,

OK, waiting for reply.

Thank you
Logged