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Author Topic: UM232H->FPGA interface (Asynchronous FIFO mode using TeraTerm and VCP drivers)  (Read 4717 times)

bbanacki

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Are there any examples demonstrating how to interface between the FTDI UM232H evaluation board with an FPGA? 

We would like to use the the Asynchronous FIFO mode along with the Virtual COM Port (VCP) drivers.  I was hoping FTDI could provide an example or offer some guidance that would allow TeraTerm to be used to send bytes to the FPGA and have the FPGA simply mirror them back. Once this communication bridge is established our development time can be spent on the actual message processing.  This seems like a common design that may have already been done.
 
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FTDI_USA

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You can find all the details on interfacing with our FIFO ICs in Tech Note TN_167:
https://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_167_FIFO_Basics.pdf

Best Regards,

FTDI USA Support
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bbanacki

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I have read the FIFO basics document and found the Verilog example for an 8-bit counter but correct me if I'm wrong it demonstrates synchronous mode which can only be used with the D2xx drivers. The example only demonstrates how to write to the output, I was looking for something that would exercise both read and write in asynchronous mode using the VCP drivers so something like TeraTerm could be used to test the interface.  I thought a loop-back Verilog example may already exist as it would help get the development started quickly as it's the first step before adding custom logic to process the data inputs and outputs. 
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FTDI_USA

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Correct, the Verilog example in the tech note was designed for Sync FIFO.
Afraid we don't have an Asynchronous FIFO loop back example in Verilog.

For the Asynchronous FIFO example in TN_167, one channel of our FT2232H was used in bit-bang mode, and the receiving channel was configured as Asynchronous FIFO.  The  Asynchronous FIFO WR input was toggled by an external function generator.

Best Regards,

FTDI USA Support
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