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Author Topic: FT601Q Write transaction issue from FT601 master (FPGA) to FT601 USB IN channels  (Read 142 times)

StavrosKouvaris

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Hello,

I have an issue while trying to set up communication between my FPGA and a PC usb interface. I use the FT601Q USB3.0 chip on 4-channel mode. While i have no issues in transferring data from the PC to the FPGA using the chip, i cannot set up functional digital logic for transfering data from FPGA to PC. Obviously, the FPGA is the FT601Q master. I am trying to build my FSM (Finite state machine) according to the figure 4.4 of the FT601Q datasheet. My VHDL code for a basic write transaction from FPGA to PC via channel 1 is shown below:

MAIN: process(ft601q_clk, resetn, data_state, DATA, rxf_n)
    begin
        if(resetn = '0') then
            data_state <= IDLE;
            DATA(31 downto 16)  <= (others=>'1'); 
            DATA(7 downto 0)     <= (others=>'1');
            DATA(15 downto 8)   <= (others=>'Z');
            BE(3 downto 0)         <= (others=>'1');
            wr_n <= '1';
        elsif(rising_edge(ft601q_clk)) then
            case data_state is
                --------------------------------------------------------------------------------
                ----------- IDLE STATE: FSM waits for DATA(8) to be asserted ------------
                when IDLE =>
                    DATA(31 downto 16) <= (others=>'1'); 
                    DATA(7 downto 0)     <= (others=>'1');
                    DATA(15 downto 8)   <= (others=>'Z');
                    BE(3 downto 0)        <= (others=>'1');
                    wr_n  <= '1';
                    if(DATA(8) = '0') then
                        data_state <= CONFIG_WRITE;
                    else
                        data_state <= IDLE;
                    end if; 
                -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
                --------- CONFIG WRITE STATE: the writing command is configured. Writing channel is channel 1. When rxf_n is asserted DATA(31 downto 0) is driven to ones ---------
                when CONFIG_WRITE =>
                    wr_n <= '0';
                    if (rxf_n = '1') then                                                             
                        BE <= "0001";
                        DATA(7 downto 0) <= "00000001";
                        DATA(15 downto 8)  <= (others=>'Z');
                        DATA(31 downto 16) <= (others=>'1');
                        data_state <= CONFIG_WRITE;
                    elsif (rxf_n = '0') then
                        BE <= "1111";
                        DATA <= (others => '1');
                        data_state <= WRITE;
                    end if;
                ---------------------------------------------------------------------------------------------------------------------------------------------------------------
                ------- WRITE STATE: DATA is driven 0xFFFF until rxf_n is deasserted. Basically 0xFFFF is sent until either USB IN of channel 1 gets full --------- 
                when WRITE =>
                    wr_n <= '0';
                    if (rxf_n = '1') then
                        DATA <= (others=>'Z');
                        BE <= (others=>'1');
                        data_state <= BUS_WR_TURNAROUND;
                    elsif (rxf_n = '0') then
                        BE <= "1111";
                        DATA <= (others => '1');
                        data_state <= WRITE;
                    end if;
                 ---------------------------------------------
                when BUS_WR_TURNAROUND =>
                    DATA <= (others=>'Z');
                    BE <= (others=>'1');
                    wr_n <= '1';
                    data_state <= IDLE;     
                ---------------------------------------------                                   
            end case;
        end if;
    end process;

What the above VHDL code basically does is waiting for a  reading demand from PC (a reading demand from channel 1 by software seems necessary for DATA(8) to be set from 1 to 0). After a demand is made and DATA(8) gets equal to 0, the FPGA sends 0xFFFF continuously until rxf_n is set to 1 by the chip.

After implementing the logic, i get the following behavior: when a channel-1 reading demand is made from PC, DATA(8) is indeed asserted from 1 to 0. The FSM remains in CONFIG_WRITE state until rxf_n is set to 0. After 2 clock cycles, rxf_n is indeed driven to 0 by the FT601 chip. However, on the next clock cycle, rxf_n is deasserted (set to 1) and the only data i get on the PC is 1 byte, equal to the number of channel im working on (for channel 1 I get byte 0x1). This write transfer suspiciously matches the BE = '0001' and DATA(7 downto 0) = '00000001' and it seems like my assignements BE = '1111' and DATA(31 downto 0) = '1111...11' are one clock cycle delayed.
I dont see how i could prevent this issue as my FSM sets BE='1111' by the time rxf_n is sampled to be equal to 0. I consider important to notify that my logic is synchronous to the rising edge of the FT601Q - 100MHz clock.
Here is a screenshot from the ila vivado cores i used to track the issue -> https://prnt.sc/u4vrqk. (signal p_0_in corresponds to rxf_n)

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FTDI Community

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Hello,

Please refer to our software examples for working examples:

https://www.ftdichip.com/Support/SoftwareExamples/FT60X.htm

There are also software examples provided with the D3XX driver download.

These examples demonstrate both read and writes using FT60x.

There may be other FTDI Community users who can help further.

Best Regards,
FTDI Community
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