FTDI Community

Please login or register.

Login with username, password and session length.
Advanced Search  

News:

Welcome to the FTDI Community!

Please read our Welcome Note

Technical Support enquires
please contact the team
@ FTDI Support


New Bridgetek Community is now open

Please note that we have created the Bridgetek Community to discuss all Bridgetek products e.g. EVE, MCU.

Please follow this link and create a new user account to get started.

Bridgetek Community

Author Topic: About the input delay of FPGA when connecting FT601 with FPGA  (Read 1113 times)

StanleyChien

  • Newbie
  • *
  • Posts: 4
    • View Profile
About the input delay of FPGA when connecting FT601 with FPGA
« on: January 27, 2021, 11:49:53 AM »

Hi,

I am using the FT601 chip with Cyclone V GX FPGA.

I have difficulty in setting the input delay of FPGA's timing constraint.

In common definition of input delay, input delay = the time from clock rising to data stable (both clock and data  are from FT601).

In FT601's datasheet,  (https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT600Q-FT601Q%20IC%20Datasheet.pdf)
In Figure 4.8 and Table 4.2, T1 and T2 give the AC timing of signals from FT601 to FPGA.

It seems that the data is stable between CLK's rising-T1 to CLK's rising+T2.

There's an sdc example in AN_421 FIFO Bus Master for FT60x (https://www.ftdichip.com/Support/Documents/AppNotes/AN_421_FIFO_Bus_Master_For%20FT60x.pdf)

Code: [Select]
set_input_delay -clock [get_clocks fifoClk] -max 7.0  [get_ports {RXF_N}]
set_input_delay -clock [get_clocks fifoClk] -max 7.0  [get_ports {BE[*] DATA[*]}]
set_input_delay -clock [get_clocks fifoClk] -min 6.5  [get_ports {RXF_N}]
set_input_delay -clock [get_clocks fifoClk] -min 6.5  [get_ports {BE[*] DATA[*]}]

The input delay max = CLK period - T1 = 10ns - 3ns = 7ns (for CLK = 100MHz)



I am confused about the input delay min = 6.5ns.

Since T2 is a minimal value, after CLK's rising+T2, the data of next cycle may be stable before the next CLK's rising-T1.

So I think the input delay min is T2 = 3.5ns.

Why the input delay min is 6.5ns in the AN_421?


Thanks,
Stanley



Logged

FTDI Community

  • Administrator
  • Hero Member
  • *****
  • Posts: 660
    • View Profile
Re: About the input delay of FPGA when connecting FT601 with FPGA
« Reply #1 on: January 29, 2021, 04:42:31 PM »

Hello,

We are actively working with R&D to review FPGA timing.

Our IC designer has confirmed that the timing we are using in our demo application is a known good reference:

https://ftdichip.com/software-examples/ft600-601-software-examples/

You can also contact your local support team via email as it seems you have already been in contact before:

https://ftdichip.com/technical-support/

Best Regards,
FTDI Community
Logged

NorthGuy

  • Newbie
  • *
  • Posts: 3
    • View Profile
Re: About the input delay of FPGA when connecting FT601 with FPGA
« Reply #2 on: February 08, 2021, 09:33:45 PM »

Here's what the example application suggests for Quartus:

Code: [Select]
set_input_delay -clock [get_clocks fifoClk] -max 7    [get_ports {BE[*] DATA[*]}]
set_input_delay -clock [get_clocks fifoClk] -min 6.5  [get_ports {BE[*] DATA[*]}]

set_output_delay -clock [get_clocks fifoClk] -max 1.0 [get_ports {BE[*] DATA[*]}]
set_output_delay -clock [get_clocks fifoClk] -min 4.8 [get_ports {BE[*] DATA[*]}]

Here's what I used for Xilinx 7-series in Vivado, which I believe is correct:

Code: [Select]
# max delay is 7.0 (from FTDI docs) + 0.4 data wires - 0.2 clock wire = 7.2
set_input_delay -clock [get_clocks clk_ftdi] -max 7.2 [get_ports {ftdi_data_*}]
# min delay is 3.5 (from FTDI docs) + 0.2 data wires - 0.2 clock wire = 3.5
set_input_delay -clock [get_clocks clk_ftdi] -min 3.5 [get_ports {ftdi_data_*}]

# max delay is 1.0 (from FTDI docs) + 0.4 data wires + 0.2 clock wire = 1.6
set_output_delay -clock [get_clocks clk_ftdi] -max 1.6 [get_ports {ftdi_data_*}]
# min delay is -4.8 (from FTDI docs) + 0.2 data wires + 0.2 clock wire = -4.4
set_output_delay -clock [get_clocks clk_ftdi] -min -4.4 [get_ports {ftdi_data_*}]

The FT601->FPGA figures (set_input_delay) are easy to meet either way.

The FPGA->FT601 figures (set_output_deay) are practically impossible to meet because of the very long hold requirement. Of course, if you use "hold" instead of "minus hold" for set_output_delay -min (as in the example application) the timing analysis will succeed every time.
Logged

StanleyChien

  • Newbie
  • *
  • Posts: 4
    • View Profile
Re: About the input delay of FPGA when connecting FT601 with FPGA
« Reply #3 on: February 18, 2021, 09:37:58 AM »

Hi, NorthGuy:

Thanks for your reply!   :)

I have the same opinion with you on the min value of input and output delay.

I think your SDC is correct unless we misunderstand the FT601's datasheet.
Logged