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Author Topic: Delay Between CLK and MOSI Operation  (Read 509 times)

rudolf

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Delay Between CLK and MOSI Operation
« on: July 22, 2021, 06:14:30 AM »

Hello,

Is it possible to add delay in Mosi line for FT2232H?

I referred user guide of FT2232H in which i found that MPSSE mode has default CLK to MOSI delay operation is 1nS to 7.15nS. but how to control it? I also attached MPSSE timing diagram.

If there is another way to add delay between CLK and MOSI line, pls suggest.

Thanks in advance.
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cioma

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Re: Delay Between CLK and MOSI Operation
« Reply #1 on: July 22, 2021, 05:44:16 PM »

I don't think this timing is controllable as this is just a propagation delay between the edge of the clock signal and the change in the data signal synchronized by that clock.
And I don't think you need to control it in your design either.
What SPI device are you trying to communicate with?
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rudolf

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Re: Delay Between CLK and MOSI Operation
« Reply #2 on: July 23, 2021, 09:44:43 AM »

Thank you for replying!!!

I want to send commands to slave using FT2232H, in which i have to add approx. 50ns delay between CLK and MOSI line. so the slave will understand data correctly.
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FTDI Community

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Re: Delay Between CLK and MOSI Operation
« Reply #3 on: July 23, 2021, 11:05:30 AM »

Hello,

This is not possible. Is there a reason why you need it?
You should use the instructions (e.g. clock data on x edge) so that you change data on the edge which is not the valid one and in this case would normally not be an issue.   

Which SPI mode does your SPI peripheral use? Note that MPSSE only supports mode 0 and 2.
Mode 1 or 3 is not supported.

You can also try enabling 3-phase clocking.
This will give 3 phases so data is valid on both edges.

See AN_108 Command Processor For MPSSE and MCU Host Bus Emulation Modes for more details.

AN_411_FTx232H MPSSE I2C Master Example in Csharp shows an illustration of 3-phase in section 6.2.2.

Best Regards,
FTDI Community
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rudolf

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Re: Delay Between CLK and MOSI Operation
« Reply #4 on: July 23, 2021, 12:21:45 PM »

Thank you,

I am using SPI mode 1. CLK is 5 MHz for data transfer, and i measured 1 clk cycle.
1 CLK = 166ns
50% CLK = 83ns
25% CLK = 41ns.

The reason behind adding delay is to design results shows that MOSI line is shifted 25% with the CLK. so i need 41ns delay in that line.
« Last Edit: July 23, 2021, 12:34:48 PM by rudolf »
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FTDI Community

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Re: Delay Between CLK and MOSI Operation
« Reply #5 on: July 23, 2021, 04:39:24 PM »

Hello,

SPI Mode 1 is not supported with the MPSSE engine.

Please consider FT4222H which supports all SPI modes.

Best Regards,
FTDI Community
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