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Author Topic: Can RD# be shorted to OE# in Sync 245 FIFO?  (Read 474 times)


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Can RD# be shorted to OE# in Sync 245 FIFO?
« on: March 28, 2022, 07:50:00 PM »

I have understood the purpose of both RD# and OE# but they seem to be redondant in the logic of sync 245 fifo. OE# is pulled down by the FPGA one cycle before RD# so they are moving low in synchronization (with one cycle difference).

Can RD# be shorted to OE#? The FPGA will obviously know that the valid byte comes one cycle after the low event. And they go up at the same time which doesn't impact the FPGA and hopefully shouldn't confuse the FTDI chip.

The purpose of this operation is to save one pin on the FPGA side.

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Re: Can RD# be shorted to OE# in Sync 245 FIFO?
« Reply #1 on: March 29, 2022, 04:39:20 PM »

Hi Gregg,

Don’t do this – OE needs to be controlled by a separate signal from the downstream FPGA.

RD# needs to be throttled by the FPGA according to the state of the RXF# flag.

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