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Author Topic: Support different maximum clock frequency on UMFT4222EV and FT4222HQ  (Read 11220 times)

TonySH

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Hi experts,
    I got a FTDI device module UMFT4222EV-D, my target are using a GPIO pin and a channel SPI with clock running as 40M Hz.
    So, I looked up the data sheet of the module UMFT4222EV and chipset FT4222, and found it supports different maximum clock frequency.

    In the "UMFT4222EV - USB2.0 to QuadSPI/I2C Bridge Development Module Datasheet Version 1.4" from the FTDI website.
   
Quote
3 FT4222H Features and Enhancement
...
The max SPI interface operating clock can be set up to 30MHz in master mode and 20MHz in slave mode.
...

    In the "FT4222H USB2.0 TO QUADSPI/I2C BRIDGE IC Datasheet Version 1.5" from the FTDI website.
   
Quote
4.1 Key Features
...
The maximum SPI interface operating clock can be set up to 40MHz in master mode and 20MHz in slave mode.
...

    There is 10MHz lost on UMFT4222EV-D device in master mode, what's going on the device? and for my target, which device I can use? Is there a suggestion?
   
Thanks
TonySH
« Last Edit: May 17, 2024, 01:06:53 pm by TonySH »
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FTDI Community

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Hello,

I can confirmed that the maximum SCK in SPI Master mode is 40MHz.

We will update the UMFT4222EV datasheet.

Best Regards,
FTDI Community
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TonySH

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Hi experts,
    Thanks for your confirmation.

    About the library "LibFT4222" I used, I also need to double check with you, LibFT4222 supports the SCK performed with 40 MHz in SPI master mode, is that right?

Thanks
TonySH
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FTDI Community

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Hello,

Yes you can use FT4222_SetClock to set the system clock to 80MHz, then use FT4222_SPIMaster_Init and set clock_div to CLK_DIV_2 (1/2 System Clock) which should give 40MHz on SCK.

Please make sure you are using the latest version of LibFT4222:

https://ftdichip.com/software-examples/ft4222h-software-examples/

And reference AN_329 User Guide for LibFT4222.

Best Regards,
FTDI Community
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TonySH

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Hi experts,
     I got it, thank you.
     
     BTW, I got an issue that using SPI 30M Hz in master mode works for our application, but it doesn't work on 40M Hz, the way of configuration is the same as you mentioned.
     The issue is that the data the Host received is wrong.

     I will look up the signals of CLK, MOSI and MISO on the oscilloscope first, then report to you on the other thread if the issue is still there.

     Thanks again.

Best Regards,
TonySH
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FTDI Community

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Hello,

Sure if you try system clock to 60MHz, then use FT4222_SPIMaster_Init and set clock_div to CLK_DIV_2 (1/2 System Clock) which should give 30MHz on SCK.

Your issue could be weak SPI signals when you configure clock to 30MHz or 40MHz.
You can try adding pull high resistor on the SPI pins especially the clock.

If you are still having issues contact our Taiwan Support team:

tw.support1@ftdichip.com

Best Regards,
FTDI Community
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