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General Discussion / Re: FT82x
« on: October 31, 2018, 01:30:11 PM »
Hello,
If we take the example from the following WQVGA settings:
HCYCLE = 928
VCYCLE = 525
VCYCLE * HCYCLE = 487,200
Note: REG_PCLK is using the value 2 which will divide the clock down to 30Mhz.
Result = 30,000,000/487,200 = ~ 61
The intention in this example is to get the refresh rate at or near 60 fps, but if your display can support higher PCLKs then a higher refresh rate should be possible.
Best Regards,
FTDI Community
If we take the example from the following WQVGA settings:
Code: [Select]
// WQVGA display parameters
lcdWidth = 800; // Active width of LCD display
lcdHeight = 480; // Active height of LCD display
lcdHcycle = 928; // Total number of clocks per line
lcdHoffset = 88; // Start of active line
lcdHsync0 = 0; // Start of horizontal sync pulse
lcdHsync1 = 48; // End of horizontal sync pulse
lcdVcycle = 525; // Total number of lines per screen
lcdVoffset = 32; // Start of active screen
lcdVsync0 = 0; // Start of vertical sync pulse
lcdVsync1 = 3; // End of vertical sync pulse
lcdPclk = 2; // Pixel Clock
lcdSwizzle = 0; // Define RGB output pins
lcdPclkpol = 1; // Define active edge of PCLK
HCYCLE = 928
VCYCLE = 525
VCYCLE * HCYCLE = 487,200
Note: REG_PCLK is using the value 2 which will divide the clock down to 30Mhz.
Result = 30,000,000/487,200 = ~ 61
The intention in this example is to get the refresh rate at or near 60 fps, but if your display can support higher PCLKs then a higher refresh rate should be possible.
Best Regards,
FTDI Community