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Discussion - Software / Re: Delay Between CLK and MOSI Operation
« on: July 23, 2021, 12:21:45 PM »
Thank you,
I am using SPI mode 1. CLK is 5 MHz for data transfer, and i measured 1 clk cycle.
1 CLK = 166ns
50% CLK = 83ns
25% CLK = 41ns.
The reason behind adding delay is to design results shows that MOSI line is shifted 25% with the CLK. so i need 41ns delay in that line.
I am using SPI mode 1. CLK is 5 MHz for data transfer, and i measured 1 clk cycle.
1 CLK = 166ns
50% CLK = 83ns
25% CLK = 41ns.
The reason behind adding delay is to design results shows that MOSI line is shifted 25% with the CLK. so i need 41ns delay in that line.