FTDI Community

General Category => Discussion - Hardware => Topic started by: Magip on September 29, 2020, 05:18:25 AM

Title: FT602: How does individual WR_N transactions becomes 1 bulk packet?
Post by: Magip on September 29, 2020, 05:18:25 AM

Hi,
  I have successfully ported pattern generator example to my custom PCBA and I can see vertical colour bars on PC.  I am studying the how the UVC header and data is being sent from FPGA using WR_N transactions.  I also used Wireshark to capture USB tranffic and observe that multiple WR_N transactions are consolidated into 1 USB bulk transfer of size 12 bytes (header) + 640x480x2 bytes (yuy2 data).

  I am confused by how FT602 knows which of the WR_N transaction is the start of UVC frame and which is the last?  What is the purpose of sending data = 0x00000055 and BE = 0x1 and the end of yuy2 data?  This 0x55 byte is not captured by Wireshark even though it is sent by FPGA to FT602.

Regards,

Magip

Title: Re: FT602: How does individual WR_N transactions becomes 1 bulk packet?
Post by: FTDI Community on September 29, 2020, 03:12:33 PM

Hello,

It can tell the end of the data by the BE (byte enable) signals. The 0x55 is an arbitrary value and is not actually accepted into the FIFO and so the value is not important.

The bus master asserts the signal for the valid bytes in a word strobe. Normally, all 4 bytes should be valid in a bus transaction except in the last word strobe when the data transaction length is not aligned at a word boundary. When BE[3:0]=0001 the FT602 knows that it is the end of data. The FT602 will also then see the header of the next frame and knows that the last frame has ended.

Best Regards, FTDI Community