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Messages - FTDI_USA

Pages: [1]
Discussion - Software / Re: FT2232H random error on one channel
« on: May 19, 2021, 09:21:51 PM »

Have not yet received your design schematic.

Please send it to us.support@ftdichip.com in PDF format.

Are you using the FT2232HQ or FT2232HL chip?

Best Regards,
Cameron Forbes,  FTDI USA Customer Engineering

Discussion - Software / Re: FT2232H random error on one channel
« on: May 18, 2021, 06:19:13 PM »

What version of the Linux kernel are you using?

What baud rate are you using?

How much data are you transferring per session?

Are you using a Linux TTY such as PuTTY, or you own Linux COM port code?

Please send your design schematic to  us.support@ftdichip.com

Best Regards,

Cameron Forbes, FTDI USA Customer Engineering

Discussion - Software / Re: FT260 UART-HID bridge problems
« on: April 22, 2021, 07:02:26 PM »

What OS are you using to talk with the FT260?

If you are running Windows, we offer the LibFT260 dll for configuring/communicating the FT260 as a USB-HID to UART bridge:

Best Regards,
FTDI US Support

Discussion - Hardware / Re: Connecting unused pins on the VNC1L?
« on: October 26, 2020, 08:45:49 PM »

The unused pins on the VNC1L can be left floating.

Answer:  The unused pins on the VNC1L can be left floating.

Also keep in mind the VNC1L only offers “managed mode” SPI Slave functionality, while the VNC2 supports both SPI Master and SPI Slave in unmanaged mode.

Best Regards,

New Member Introductions / Re: Hello from the Netherlands
« on: October 20, 2020, 05:59:09 PM »

The following applications note describes the programming protocol for the VNC2:

Feel free to continue our conversation by email:

Best Regards,



The VNC1L SPI interface is only available as a SPI slave and uses "managed mode" SPI, which is not commonly used.

The VNC2-32L1C can be configured as a SPI slave or master, and supports "unmanaged SPI", which makes it compatible with industry standard SPI interfaces.

Feel free to contact me via  us.support@ftdichip.com  going forward.

Best Regards,


Correct, the Verilog example in the tech note was designed for Sync FIFO.
Afraid we don't have an Asynchronous FIFO loop back example in Verilog.

For the Asynchronous FIFO example in TN_167, one channel of our FT2232H was used in bit-bang mode, and the receiving channel was configured as Asynchronous FIFO.  The  Asynchronous FIFO WR input was toggled by an external function generator.

Best Regards,

FTDI USA Support

You can find all the details on interfacing with our FIFO ICs in Tech Note TN_167:

Best Regards,

FTDI USA Support

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