Is there any updates on this topic? Because provided documents does not answer where this configuration option can be found and how to use it?

Hi,

i am having difficulties running FT601 with 66MHz FIFO clock setting in Multi-Channel FIFO mode. We are using our custom board and example design for Altera FPGA.

I am using timing constraints provided in example design and example runs fine with 100MHz FIFO clock, but when i change FIFO clock setting (in configuration utility) to 66MHz example design does not work. I have tried editing timing constraints file for FPGA and change clock period from 100Mhz to 66 MHz but this does not help. 

Is there anything else has to be changed to make example design work with 66Mhz FIFO clock?