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Messages - FTDI Community

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Hi Tony,

Your only option would be to add some external pulldown on the GPIOH pins. Even if they have been set as low and input, if there is no connection they will be pulled high by the internal pullups.

Best Regards
FTDI Community

Hi Tony,

The default for these GPIO pins is TriSt-PU. See table 5.1 in FTDI Device Input Output pin States.

what are you planning on connecting the GPIOH pins to? have you tried connecting the pins to a slave device and performing a GPIO read?

Best Regards
FTDI Community

Discussion - Software / Re: FT2232hpq
« on: April 10, 2024, 10:20:45 AM »

When using LibMPSSE, GPIOL[0:3] can only be used as SPI chip selects.
When using LibMPSSE, there is no way to control GPIOL[0:3] as GPIO.
LibMPSSE demonstrates controlling the higher line bytes (GPIOH) while using SPI on the lower line bytes using the following functions:
If you want to control some of the unused lower line bytes on the same ADBUS as SPI then see AN_411 FTx232H MPSSE I2C Master Example in C which demonstrates GPIO usage with MPSSE using D2xx direct (not using LibMPSSE).
This could be used as a base to understand using both SPI/GPIO in the same code.
OK this example is for I2C but the same principles apply to SPI.

Best Regards
FTDI Community


Please confirm which version of the D2xx driver and LibFT4222 that you are using?

Are you using custom FT4222H hardware? Do you see the same issue with our UMFT4222EV-D?

Could the I2C slave be at fault rather than the FT4222H I2C master?

When this happens maybe you can perform a software reset rather than having to force quit or restart?
See FT4222_ChipReset API. You can also try these D2xx based APIs:


Best Regards,
FTDI Community


Unfortunately the LibFT4222 source code can't be shared as it's exposes secrets of our vendor class devices.

Please contact us via email on support1@ftdichip.com and we'll contact our R&D team to see if we can provide a 64 Bit (aarch64) build.

Best Regards,
FTDI Community

Discussion - Hardware / Re: FT2232HQ adds extra one byte
« on: March 21, 2024, 03:32:52 PM »

The extra bytes may be due to lack of biasing on the RS485 transceiver. If you could email into support1@ftdichip.com we can share the RS485 biasing schematic that will be able to help you.

Best Regards
FTDI Community 


Yes, there are internal pullups on the RXD lines of FT232R and FT232H.

the typical value is 75 KΩ. You can find more information in 5.3 of the FT232H datasheet.

Best Regards
FTDI Community

General Discussion / Re: Question
« on: March 14, 2024, 10:52:13 AM »

Number 1 is just the general configuration of the device. Number 2 is to enable the GPIOs. Have a look at section 3.1 of AN_412 FT600/FT601 Bridge Chips Integration.

This goes over the configuration modes of FT600 with section 3.1.5 focusing on the GPIO configuration.

We have a FT60x configuration programmer that you can use. You can find it here along with the AN_370 FT60X Configuration Programmer User Guide.

Best Regards
FTDI Community

General Discussion / Re: Question
« on: March 14, 2024, 09:41:41 AM »

Have a look at section 3.2 of AN_412 FT600/FT601 Bridge Chips Integration, this goes over the abort recovery process.

Any error or timeout requires this abort process before resuming the read/write.

Best Regards
FTDI Community

Test and Review Area / Re: LibMPSSE Beta
« on: February 29, 2024, 02:13:46 PM »
Hello All,

LibMPSSE 1.0.5 fixes all known issues and is available on our website:


Best Regards,
FTDI Community

Discussion - Software / Re: FT_Read method for SPI communication
« on: February 29, 2024, 02:06:05 PM »

We don't have any references for doing SPI communication using Bit-Bang. I would recommend that you use the MPSSE for SPI communication instead.   

To use I2C/SPI as a master (no slave functionality), see AN_135 MPSSE Basics and our existing MPSSE Example projects:
MPSSE Examples
There are two options to use I2C/SPI modes with the MPSSE engine:
a.   Use LibMPSSE libraries. Example code is provided with the download. Source code is also provided.
b.   Use D2XX drivers direct. Example code is shown at I2C / SPI. AN_108 Command Processor For MPSSE and MCU Host Bus Emulation Modes provides the necessary information.
Option b is the best option to use the D2XX drivers direct (no dependency on libMPSSE library).

Also please also note, SPI modes 1 and 3 are not supported with our MPSSE engine.
So please check that your SPI device doesn’t work with these modes.

You can find all the referenced documentation above, here

Discussion - Hardware / Re: FT602Q video pin map question!!
« on: February 29, 2024, 02:03:51 PM »
Hi Joseph,

All of the formats supported by FT602 can be found on page 13 of the FT602_UVC_Chip_Configuration_Guide.

There are no signals like VSYNC/HSYNC/PCLK on FT602. FT602 is connected via an FPGA.

You can refernce the FT602 example code, which you can find here. The example code shoes YUV only, but you can use it for a reference for the other formats.

Discussion - Hardware / Re: Fastest I2C transfer rate on FT2232HQ?
« on: February 14, 2024, 04:42:46 PM »

yes, FT2232H is a high-speed device. The driver can only operate with 1ms latency minimum.

Best regards
FTDI Community

Discussion - Hardware / Re: Fastest I2C transfer rate on FT2232HQ?
« on: February 13, 2024, 02:02:36 PM »

You can try setting the latency timer to 1ms. This will make the device ran as fast as it can.

Best Regards
FTDI Community

Discussion - Hardware / Re: FT600q communication problem
« on: January 19, 2024, 04:19:30 PM »

There are 2 kinds of delays / pauses.

1. Occurs when FIFO switches from ping to pong buffer. There are 2 FIFO Buffers and when current one gets filled, hardware moves to second FIFO. There will be a brief delay during this period.
2. Occurs when a session is ended and a new session is created. This delay can be slightly larger than the above one.
A session will be ended when the length of transferred data equals with the stream length set by FT_SetStreamPipe API (if not in stream mode, then the length passed in Read Pipe API), or when an unaligned write happens.
Between the end of session and start of new session, there could be some delay as observed.

If the stream length is shorter, this delay will be seen often.
The recommended stream length is, several multiples of the FIFO size.
For example, if the FT600 configuration uses 4K FIFO size, it's best to make the stream length as multiples of 4K - Say 10 times or 100 times of 4K.
This way, instead of seeing a long delay every 4K, the long delay will happen only at 400K transfer boundaries.

The FPGA is expected to buffer at least a FIFO size worth of data so that the delay does not cause any issues such as overflow.

If you have any additional questions please contact us via email as we have already been in contact with you.

Best Regards,
FTDI Community

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