FTDI Community

Please login or register.

Login with username, password and session length.
Advanced Search  

News:



Welcome to the FTDI Community!

Please read our Welcome Note

Technical Support enquires
please contact the team
@ FTDI Support


Author Topic: FT601 on Cyclone V GX  (Read 91 times)

alrsir

  • Newbie
  • *
  • Posts: 2
    • View Profile
FT601 on Cyclone V GX
« on: November 27, 2018, 02:11:06 PM »

Hi,
I am considering using the FT601 chip with Cyclone V GX FPGA. I have purchased the Cyclone V GX starter kit and UMFT601A USB3 kit. Now I am trying to synthesize the provided examples to be used with the kit on Quartus Prime ver 17. I have noticed that all the examples have timing constrains violations if synthesized for 7 speed grade FPGA which is installed on the GX kit.  I was only able to remove timing violations if I choose 6 speed grade chip, but it is not the chip which is used on the Altera/Intel kit.

Is there something wrong with the examples?

Thanks,
Alexey.
Logged

FTDI Community

  • Administrator
  • Full Member
  • *****
  • Posts: 184
    • View Profile
Re: FT601 on Cyclone V GX
« Reply #1 on: November 28, 2018, 11:21:35 AM »

Hello,

We provide images for the Xilinx Spartan-6, Virtex-6 and Altera Cyclone V. See the following Programming Guides for further information:-

AN_376 - Xilinx FPGA FIFO master Programming Guide
http://www.ftdichip.com/Support/Documents/AppNotes/AN_376 Xilinx FPGA FIFO master Programming Guide.pdf
AN_377 - Altera FPGA FIFO master Programming Guide
http://www.ftdichip.com/Support/Documents/AppNotes/AN_377 Altera FPGA FIFO master Programming Guide.pdf

User Guides for the Data Loopback and Streamer examples may be found here:

AN_375 - FT600 Data Loopback Application User Guide
https://www.ftdichip.com/Support/Documents/AppNotes/AN_375 FT600 Data Loopback Application User Guide.pdf

AN_387 - FT600 Data Streamer Application User Guide
https://www.ftdichip.com/Support/Documents/AppNotes/AN_387 FT600 Data Streamer Application User Guide.pdf

As Im sure you are aware Software examples are here:

http://www.ftdichip.com/Support/SoftwareExamples/FT60X.htm

For API information, please review the D3XX Programmer's Guide
https://www.ftdichip.com/Support/Documents/AppNotes/AN_387 FT600 Data Streamer Application User Guide.pdf

We have an Application Note that describes the FPGA design of an example FIFO master that is interfaced to an FT60x device which may assist you, it’s available here: AN_421 FIFO Bus Mater for FT600 / FT601 - http://www.ftdichip.com/Support/Documents/AppNotes/AN_421_FIFO_Bus_Master_For FT600_FT601.pdf

Please refer to AN_412 FT600/FT601 Bridge Chips Integration - http://www.ftdichip.com/Support/Documents/AppNotes/AN_412_FT600_FT601 USB Bridge chips Integration.pdf. This application note is for designers who want to integrate the FT60x into new designs. As well as this have a look at our FT600Q-FT601Q SuperSpeed USB3.0 IC Datasheet - http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT600Q-FT601Q IC Datasheet.pdf and Technical Note TN_168 FT600_601 Errata Technical Note - Technical Note TN_168 FT600_601 Errata Technical Note . We also have an Application Note that describes the FPGA design of an example FIFO master that is interfaced to an FT60x device which may assist you, it’s available here: AN_421 FIFO Bus Mater for FT600 / FT601 - http://www.ftdichip.com/Support/Documents/AppNotes/AN_421_FIFO_Bus_Master_For FT600_FT601.pdf

If you have further questions it may be easier to direct them to email support here support1@ftdichip.com

Regards,
FTDI Community
Logged

alrsir

  • Newbie
  • *
  • Posts: 2
    • View Profile
Re: FT601 on Cyclone V GX
« Reply #2 on: November 28, 2018, 01:58:54 PM »

Hello,

We provide images for the Xilinx Spartan-6, Virtex-6 and Altera Cyclone V. See the following Programming Guides for further information:-

AN_376 - Xilinx FPGA FIFO master Programming Guide
http://www.ftdichip.com/Support/Documents/AppNotes/AN_376 Xilinx FPGA FIFO master Programming Guide.pdf
AN_377 - Altera FPGA FIFO master Programming Guide
http://www.ftdichip.com/Support/Documents/AppNotes/AN_377 Altera FPGA FIFO master Programming Guide.pdf

User Guides for the Data Loopback and Streamer examples may be found here:

AN_375 - FT600 Data Loopback Application User Guide
https://www.ftdichip.com/Support/Documents/AppNotes/AN_375 FT600 Data Loopback Application User Guide.pdf

AN_387 - FT600 Data Streamer Application User Guide
https://www.ftdichip.com/Support/Documents/AppNotes/AN_387 FT600 Data Streamer Application User Guide.pdf

As Im sure you are aware Software examples are here:

http://www.ftdichip.com/Support/SoftwareExamples/FT60X.htm

For API information, please review the D3XX Programmer's Guide
https://www.ftdichip.com/Support/Documents/AppNotes/AN_387 FT600 Data Streamer Application User Guide.pdf

We have an Application Note that describes the FPGA design of an example FIFO master that is interfaced to an FT60x device which may assist you, it’s available here: AN_421 FIFO Bus Mater for FT600 / FT601 - http://www.ftdichip.com/Support/Documents/AppNotes/AN_421_FIFO_Bus_Master_For FT600_FT601.pdf

Please refer to AN_412 FT600/FT601 Bridge Chips Integration - http://www.ftdichip.com/Support/Documents/AppNotes/AN_412_FT600_FT601 USB Bridge chips Integration.pdf. This application note is for designers who want to integrate the FT60x into new designs. As well as this have a look at our FT600Q-FT601Q SuperSpeed USB3.0 IC Datasheet - http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT600Q-FT601Q IC Datasheet.pdf and Technical Note TN_168 FT600_601 Errata Technical Note - Technical Note TN_168 FT600_601 Errata Technical Note . We also have an Application Note that describes the FPGA design of an example FIFO master that is interfaced to an FT60x device which may assist you, it’s available here: AN_421 FIFO Bus Mater for FT600 / FT601 - http://www.ftdichip.com/Support/Documents/AppNotes/AN_421_FIFO_Bus_Master_For FT600_FT601.pdf

If you have further questions it may be easier to direct them to email support here support1@ftdichip.com

Regards,
FTDI Community

Hi,
Thank you very much for the prompt reply. I am aware of all those documents, my question was very simple, in both RTL examples provided:
1. https://www.ftdichip.com/Support/SoftwareExamples/SuperSpeed/Altera_Dataloopback_Firmware.zip
2. https://www.ftdichip.com/Support/SoftwareExamples/SuperSpeed/FT601/cyclonev_mst_fifo32_1.1.zip

there are issues with timing violations, the first one was synthesized for 5CGXFC5C6F27C6 while the FPGA kit has 5CGXFC5C6F27C7 and the second one only meets 87MHz max clock size while 100MHz clock is required.
How could it be?

Thanks,
Alexey.
Logged