FTDI Community

Please login or register.

Login with username, password and session length.
Advanced Search  

News:

Welcome to the FTDI Community!

Please read our Welcome Note

Technical Support enquires
please contact the team
@ FTDI Support


New Bridgetek Community is now open

Please note that we have created the Bridgetek Community to discuss all Bridgetek products e.g. EVE, MCU.

Please follow this link and create a new user account to get started.

Bridgetek Community

Author Topic: txe and rxe signals in FT232H  (Read 262 times)

Rajesh@sys

  • Newbie
  • *
  • Posts: 14
    • View Profile
txe and rxe signals in FT232H
« on: March 15, 2019, 01:27:33 PM »

hi,

RXE and TXE signals are dependent or independent ?


                can TXE and RXE go LOW at same time.
Logged

FTDI Community

  • Administrator
  • Full Member
  • *****
  • Posts: 238
    • View Profile
Re: txe and rxe signals in FT232H
« Reply #1 on: March 19, 2019, 08:59:38 AM »

Hello,

Do you mean RXF# and TXE#?

RXF#:
When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by driving RD# low. When in synchronous mode, data is transferred on every clock that RXF# and RD# are both low. Note that the OE# pin must be driven low at least 1 clock period before asserting RD# low.

TXE#:
When high, do not write data into the FIFO. When low, data can be written into the FIFO by driving WR# low. When in synchronous mode, data is transferred on every clock that TXE# and WR# are both low.

A write operation can be started when TXE# is low.

A read operation is started when the chip drives RXF# low.

Best Regards,
FTDI Community
Logged

Rajesh@sys

  • Newbie
  • *
  • Posts: 14
    • View Profile
Re: txe and rxe signals in FT232H
« Reply #2 on: March 19, 2019, 10:33:14 AM »

thank you very much for your reply.

<RXF#:
When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by driving RD# low. When in synchronous mode, data is transferred on every clock that RXF# and RD# are both low. Note that the OE# pin must be driven low at least 1 clock period before asserting RD# low.

TXE#:
When high, do not write data into the FIFO. When low, data can be written into the FIFO by driving WR# low. When in synchronous mode, data is transferred on every clock that TXE# and WR# are both low.

A write operation can be started when TXE# is low.

A read operation is started when the chip drives RXF# low. >




i know this one.


are they independent ??


can we perform READ and WRITE at same time ?
Logged

FTDI Community

  • Administrator
  • Full Member
  • *****
  • Posts: 238
    • View Profile
Re: txe and rxe signals in FT232H
« Reply #3 on: March 20, 2019, 04:31:36 PM »

Hello,

This is not possible because D0 to D7 bidirectional FIFO data are used for both read and write operations.

Best Regards,
FTDI Community
Logged

Rajesh@sys

  • Newbie
  • *
  • Posts: 14
    • View Profile
Re: txe and rxe signals in FT232H
« Reply #4 on: April 27, 2019, 06:09:28 AM »

Thank you  :)
Logged