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Author Topic: FT4222H reset and Configuration  (Read 79 times)

JMLsystem

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FT4222H reset and Configuration
« on: September 03, 2019, 09:59:40 AM »

I'm using the FT4222H on the motherboard of our product and i have some questions about it :

1) What is the minimum low time for the RESETN signal before VCCIO rising ?

2) Does the EEPROM chip need to programmed before using the FT4222H ?
 Because when my Host access to the FT4222 through the USB port,
 in QSPI Master mode (DCNF[1:0]=00 or 11)
 i can see the SS0O chip select going low during 1.92µs,
 but there are no SCLK clock pulse, no MISO/MOSI/IO[2:3] changes (there are stuck à 0V)
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FTDI Community

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Re: FT4222H reset and Configuration
« Reply #1 on: September 03, 2019, 04:37:25 PM »

Hello,

You have contacted our support team via email with these questions.

The answer can be posted here once it's resolved to help other FTDI Community users.

Best Regards,
FTDI Community
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JMLsystem

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Re: FT4222H reset and Configuration
« Reply #2 on: September 06, 2019, 04:41:47 PM »

Responses from FTDI technical Support :

1) "Does the EEPROM chip need to programmed before using the FT4222H ?
  -> The OTP does not need to programmed before using the FT4222H.
      Please evaluate using the UMFT4222EV : this module OTP is not pre-programmed.

2) "What is the minimum low time for the RESETN signal before VCCIO rising ?"
  ->  The  minimum low time is about 5.2us

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