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Author Topic: FT4222H I2C Master Reliability Issue  (Read 4493 times)

gt5659a

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FT4222H I2C Master Reliability Issue
« on: February 08, 2021, 11:34:19 AM »

I am having communication reliability issues with the FT4222H as an I2C master (same issue in both Mode 0 and Mode 3).  I'm using the umft4222ev, bus powered, and connected to a custom design with two PCBAs connected by a cable. 

I am reading a single byte from a slave register (via a FT4222_I2CMaster_WriteEx with no stop followed by a FT4222_I2CMaster_Read).  If I repeat this single byte read operation, with an FT4222_I2CMaster_GetStatus in between to check for and correct error conditions or a busy bus/controller, I see that roughly 85 times out of 100 I get the correct result at 100 kHz clock.

If I change to the 24MHz internal clock, I see that I get about 95 correct reads out of 100.

As noted, the system has two PCBAs connected by a cable, with I2C SCL and SDA signals carried by the cable.  When I disconnect the cable (hence roughly halving the bus capacitance) I see 10000 out of 10000 correct reads.  When I look at the waveforms on an oscilloscope (with the single PCBA and with both PCBAs connected by the cable), the timings seem to be well within the I2C spec.  Most notably the 1000 ns rise time and 300ns fall time spec (for i2c @100kHz) are showing roughly 500ns and 150ns with both PCBAs connected, and roughly 300ns and 100ns when I disconnect the second PCBA and have the FT4222 read from another slave on it's same PCBA.  So this leads me to believe that the waveforms are not quite what we need to be.

I see similar behavior with multiple different slaves from at least two different vendors.  One chip employs clock stretching and I see roughly double the number of bad reads from this device.

1. What are the settings to enable the largest timing margin (anything aside from internal clock)? 
2.  Any other settings which you could suggest to help with this?
3.  Is there another USB-->I2C IC from FTDI (high speed preferred) that would allow for larger timing margins (must also support clock stretching) that you think could work better?  I am not too concerned about the data transfer time--if there were another solution (or more preferably a solution with modified settings on the FT4222H) that could get me a single byte read in ~15 to 20 milliseconds that would be fine, so long as the transactions are reliable.

Thanks.
« Last Edit: February 09, 2021, 02:32:12 AM by gt5659a »
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Re: FT4222H I2C Master Reliability Issue
« Reply #1 on: February 10, 2021, 04:30:43 PM »

Hello,

Please see the following documents for all available configurable parameters:

FT4222H Hi-Speed Quad SPI/I2C IC Data Sheet

User Guide for LibFT4222

Also check is that you have added 1K pull up resistors to SCL and SDA.
The typical value is 1K.
Our hardware engineer suggest you can adjust it from 1K to 10K ohm.
There is some useful information here:

https://www.i2c-bus.org/i2c-primer/how-i2c-hardware-works/


Maybe there are other FTDI Community users who have had a similar problem and can help you further.

Best Regards,
FTDI Community
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