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FT232H synchronous 245 FIFO slow Rate from FPGA to PC

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Hello. I used a FPGA to send data to pc with FT232H in synchrouous 245 mode. The FPGA sends 32 bytes every 1uS (then the rate is 32MB/s). The PC softeware uses the FT_Read function and The basic receiving is OK. But the date rate with Bushound to moniter is only 24.5MB/S and the nTXE signal is frequently High. It seems the FT_Read function runs slowly reading the Buffer and a thread is set for it without any othor operations in it. The most rate would be 40MB/s according to the FT232H datasheet.  So why? Thank you!

FTDI Community:

you should refer to FTDI FIFO Basics. Also, what operating system are you using?

Best Regards,

FTDI Community

My system is Windows 10. And my codes for the experiment almost the same as the example of the document. Actually, when I send only one byte from FPGA to PC (the rate is 1MB /s), the nTXE signal keeps low witout any HIGH state( I use FPGA to make a LED on once the nTXT turns HIGH only once). And the Bushound software also shows the accurate 1MB /s result. But when gradually raise the rate from only 1 byte per uS to tow bytes, three byes, four bytes and so on, the nTXE begins to show HIGT state, and with the rising of the rate, the HIGH state more frequently. The Bushound keeps showing righr rate. Howevery, when I send more than 24 bytes (24MB /s rate at this time),the Bushound gives the highest result of 24.5MB /s all the time although maybe  I  have sended 32 bytes to PC. Of course, at this time the nTXE HIGH state very frequently (the monitoring LED is almost on al the time). My feeling is that the FT_Read calling seems a little slow to move data to the reading buffer though I ' not sure if it is related to the windows system.
 Thank you.

FTDI Community:

Try setting the latency timer to 1ms, the default is 16ms.

The 245 FIFO interface should only be written to when the TXE# pin is logic 0.
The TXE# pin will go to logic 1 and back to logic 0 for every byte latched in.
If the application on the PC never reads any data the buffer on the PC (64kbytes) and the buffer on the chip will become full.
When these buffers are full the TXE# line should remain at logic 1 until the application on the PC does a read to free up some space.
Some users report TXE# goes back to logic 0 after a brief period (actually matches latency timer).
This can result in data loss due to overrun.
To prevent this from happening the application on the PC should have set flow control for RTS_CTS flow control.
Although the hardware does not have RTS/CTS pins the driver does not know this, but it is now forced to monitor certain status bits, which allows the TXE# pin to be kept at logic 1 until space is made available.
Best Regards

FTDI Community

I have tried in this way. But things changed nothing! I doubt if it is related to the run speed of the FT_Read function. Or the shifting speed of the FIFO. And would you please show me an example or a testing program for the streaming speed? And I have set a dedicated thread for the reading but it doesn't work too  : :'(
Best regards


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