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Discussion - Hardware / Re: Problems with UMFT601X-B, trying to connect it to KC705 (Kintex-7 board)
« on: December 28, 2017, 09:50:53 AM »
Hi!
I decided to write a little bit about my experience of working with UMFT601X-B from FPGA developer´s point of view. There is not much information on the web, so it may be useful for someone who is planning the work with this chip or having certain problems.
Below there will be a small summary and a piece of advice for FPGA designers.
Merry X-Mas and Happy New Year to everyone!
Best Regards,
Anton
I decided to write a little bit about my experience of working with UMFT601X-B from FPGA developer´s point of view. There is not much information on the web, so it may be useful for someone who is planning the work with this chip or having certain problems.
Below there will be a small summary and a piece of advice for FPGA designers.
- The device can be configured via jumpers or application FT600ChipConfigurationProg. But jumpers´ settings only take place for default configuration. That means that if you (or someone else) write some settings through FT600ChipConfigurationProg, than the configuration becomes custom and jumpers’ settings are ignored. Be careful. I spent a lot of time trying to figure out, why the device does not behave according to FT245 mode, which I had set on jumpers. I did not know, that the programmer, who worked with the device before me, made a little change in the configuration using FT600ChipConfigurationProg, so the configuration became custom and my jumper settings were ignored, the device was actually in FT600 mode…
- Use USB3. It is not only about speed, it works differently. I started with USB2, than I activated option “Keep FIFO clock ON in suspend” and than I had a lot of problems (described above in details).
- Read all the documentation, especially FT600/FT601 Errata Technical Note
- UMFT601X-B is a slave, in FPGA there must be FIFO master. There is an FPGA project for testing loopback and a certain stream test with sources available. But IMHO sources are not user-friendly; integrating user code is a really hard task. For me it appeared easier to make my own FIFO master from zero. I implemented FT245 mode (it is easier).
- The interface works fine and stable for me (I implemented it on KC705 and KCU105 boards). It may seem from the diagrams, that the data from the device should be registered on the rising edge of clock, and the data to device (and flags) must be set on the falling edge. But actually everything works on the rising edge.
- Do not forget about Resetn signal! It goes from FPGA to UMFT601X-B and if you forget about it, it may put the device into Reset state.
- FTDI support may help, they are cool guys
- A suggestion to the FTDI team: do not delete the option “Keep FIFO clock ON in suspend” from FT600ChipConfigurationProg, it is really convenient for FPGA to have a running clock all the time regardless of the data transmission! It would be nice to have this option in future for both USB3 and USB2.
Merry X-Mas and Happy New Year to everyone!
Best Regards,
Anton